Non-volatile random access memories typically comprise a latch having two branches, each branch including the source-to-drain channel of a FATMOS transistor including a floating gate overlying the drain and means permitting electron tunneling between the drain and the floating gate through the intervening insulation, each branch further including a series load device connected to the drain of the FATMOS transistor at a node therebetween. Each FATMOS transistor includes a control gate overlying the floating gate. Latching feedback is provided by connecting the control gate of the FATMOS transistor of each branch to the node of the opposite branch. The logic state of the latch is established by holding one node at a high voltage and holding the other at a low voltage, each of these voltages representing the logic bit to be stored and the complement of the logic bit to be stored, respectively. Thus, a logic 1 would be established by holding one node at a high voltage and holding the other node at a low voltage, while a logic 0 would be established by holding the one node at a low voltage and the other at a high voltage respectively. Non-volatile storage of a logic bit is accomplished by increasing the voltage applied across each of the branches so that electrons tunnel to one of the floating gates and, in some cases, discharge from the other floating gate. The result is that the threshold voltage of one of the FATMOS transistors is increased relative to the threshold voltage of the other FATMOS transistor. Thus, when the voltage applied to the latch is turned off, the information to be stored is not lost. Instead, when voltage is reapplied to the latch, the latch will assume a specific logic state dictated by the imbalance between the threshold voltages of the two FATMOS transistors.
A significant disadvantage of the latch is that the non-volatile data storage achieved through the threshold voltage imbalance between the two FATMOS transistors causes the latch, after a loss of power, to be powered up into the complement of the logic state previously stored on the latch. Accordingly, additional circuitry must be provided to complement the inverted logic state which the latch assumes when power is reapplied. Such additional circuitry consumes additional space on the semiconductive substrate on which the random access memory is formed, a significant disadvantage.